Web Reference: Nov 4, 2018 · You have a two dimensional array with elements that are of an array type. You've only covered the two dimensions and not the array elements. The element type of the aggregate is unsigned and not std_ulogic. To include the elements (others => (others => (others => '0'))). What do you mean when you ask about initialisation? Is the above code snippet answering your questions? This question is closed. Nov 5, 2017 · In this post, we describe the VHDL implementation of a MUX using the CASE-WHEN statement. Another compact and elegant way for describing a MUX architecture in VHDL is to use the array approach. In the VHDL code below is reported the VHDL code of the implementation of an 8-way MUX.
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